In this example, the circuits surrounding the filter block are sinusoidal signal generation blocks, along with virtual oscilloscopes to view in input and output. Output signals can be terminated with virtual oscilloscopes and spectrum analyzers to view both time and frequency domain responses. Within Simulink, it is easy to add virtual sources, like sine wave sources, modulated sources, or even noise-like signal. The filter parameters are set in the filter GUI. To build a filter, the designer, the designer drags the filter block from the blockset library. Building a FIR Filter using DSP Builder advanced blockset library. Figure 1 illustrates a FIR filter in the DSP Builder advanced blockset library.įigure 1. We use it here to explore the productivity benefits afforded by the next generation of Simulink synthesis tools. This example can be extended to other applications such as FFTs, digital up and down conversion, and other common processing-intensive DSP applications.īuilding a multi-channel, complex FIR filter using SimulinkĪ FIR filter is the workhorse of many DSP designs. As an example, we use a multi-channel, complex filter with changing design specs. The remainder of this article illustrates the design productivity advantages of using such tools. The second generation of system design tools developed by FPGA vendors are beginning to incorporate such functionality. Such a tool would enable designers to make system-level modifications by editing high-level constraints, and synthesize optimized HDL with the click of a button.
A tool that can automatically implement pipelining, register insertion, time-division multiplexing of scarce MAC resources, and other optimizations necessary for truly optimized HDL. What is needed is a tool that understands both the underlying FPGA architecture and the top-level system constraints. This hardware designer must make sure that the design meets timing requirements, is time division multiplexed (TDM) to maximally utilize resources, and has the control plane logic necessary to move data in and out of the data path.
Until now, the creation of an optimized HDL netlist has been a largely manual process, usually done by a different person than the algorithm designer.
While these blocksets are useful, DSP designers have lacked an optimized method to transform the Simulink design into an FPGA platform. These vendors have created blockset libraries that enable Simulink designs to be synthesized to an FPGA implementation. Simulink is popular among DSP designers, and FPGA vendors have taken note.